Business Line Description
As a technology leader, NXP is re-imagining how we connect and interact with our advanced portfolio of wireless solutions. Our in-house experts build on decades of leadership in WiFi Digital Baseband technology to not only guide the ongoing expansion of wireless, but also innovate across the entirety of the wireless spectrum. From the early days 802.11B, 11A, 11G, 11N, 11AC, to the latest 802.11AX (Wi-Fi 6) the NXP team is driving global market adoption of these successive cutting-edge technologies. When combined with the processing power of the EdgeVerse platform, NXP is uniquely positioned to enable smart connected devices for IoT, industrial, auto and communication infrastructure applications - making lives easier, safer, and more convenient.

Joining the NXP Wireless Connectivity team means you will have unparalleled opportunities to develop best-in-class products with the latest IEEE standards in advanced processing nodes; it means you will work with a group of passionate and talented engineers to tackle the most crucial tasks leading the next-generation of innovations including Wi-Fi 7 technologies.

NXP’s Wireless Connectivity team has an open and inclusive work environment that promotes excellence, innovation, collaboration, and integrity. An expanding business comes with tremendous career opportunities which will challenge and grow your talents. If you are ready to start the next chapter of your career in the wireless area, you don’t want to miss this opportunity to join a world leader in this technology.

Job Summary:

Looking for a motivated DSP ASIC Design Engineer to work on design and verification in 802.11 wireless communications IPs for NXP Semiconductor wireless network products.

As a member in our Wi-Fi Connectivity Digital Design team, the candidate will be responsible for the design and verification of our IPs. Duties include but not limited to the following areas:

• Block level micro-architecture design, RTL coding, verification, and documentation
• Area/power optimization, and design trade-off analysis
• Verification environment development and chip level verification planning and execution
• Block and chip level synthesis, timing closure and formal verification
• Chip bring-up and validation support

The candidate will work closely with the DSP systems engineers to understand the DSP systems design specifications of the assigned IP, and to work with the technical leads and other design engineers on the micro-architecture and interface requirements, and to work independently to design and verify the IP.

Key Challenges:

Working on building wireless communication systems IPs requires a strong understanding of the protocol, the system specifications, micro-architecture, area and power tradeoff, front end design and back end design, silicon validation, and system level issue debugging. In addition, the Digital Design Engineer also will have the opportunity to expose to working knowledges in RF and Analog IPs, for example antennas, low noise amplifiers, mixers, low pass filters, power amplifiers, ADC, DAC, PLL, etc.

The work can be a challenge as there are so many things to learn in such a wide area of domains that it may takes years of practice to become an expert in this field. It not only requires learning many domain knowledges, various basic tools, and many hands on experience in design, verification, and mastering the ASIC flows, it also needs strong analytic capability and perseverance to strive in all kind of issues handling.

Cross functional aspects:

Working in the chip industry like NXP will expose you to experts in hardware, firmware, software, and the DSP communications and systems. The position will require interfacing with DSP systems experts, RF engineers, MAC engineers, SoC design engineers, Design Verification Engineers, firmware and software engineers, and hardware engineers.

The position requires participations in all stages of WiFi systems development, from the design specification, the RTL design and verification in block level, verification in SoC level, synthesis and timing closure, tapeout, silicon validation, and customer issue debugging support. You will have the opportunity to interact with different domain experts and to gain experiences and to excel from these interactions and learning.

Job Qualifications:

• The candidate must possess a Master of Science in Electrical Engineering or Computer Engineering
• Up to 2 years work experience, including internships
• Additional qualifications include:
  • Course works in VLSI and Digital Designs
  • Understanding ASIC design flow
  • Experience in micro-architecture design, RTL coding, and functional verification
  • Good understanding of synchronous/asynchronous design, and timing requirements for complex IP modules
  • Experience in Verilog HDL and Verilog design tools (Synopsys VCS, Verdi or similar) is required
  • Working knowledge of binary number format and its operation is required
  • Good understanding of DSP and Wireless Communication Systems/Algorithms is a plus
  • Experience in system Verilog is a plus
  • Strong verbal and written communications including the ability to write design documentation and verification plans
• Familiarity with following common digital design tools is very helpful:
  • Verilog design tools (Synopsys VCS, Verdi or similar)
  • Synthesis tools (Synopsys Design Compiler)
  • Lint, CDC tools (Synopsys Spyglass or similar)
  • Static Timing Analysis tools (Synopsys PrimeTime)
  • Power estimation tools (Synopsys PTPX, Spyglass, Cadence Joule or similar)
  • Hardware validation tool (Palladium, FPGA etc.)
  • Handy with common scripts (shell, Perl etc.)
  • Handy with laboratory debug tools on chip support (Logic Analyzer, Oscilloscope)

Job location:
• 350 Holger Way, San Jose, CA

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.