Job Details:

Job Description:

As part of Design Enablement's Library and Technology team you will join a highly motivated group of top-notch engineers solving challenging technical problems in physical design pathfinding.

Your responsibilities will include, but are not limited to:

• Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.
• Determines architecture design, logic design, and system simulation.
• Defines module interfaces/formats for simulation.
• Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.
• Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
• Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
• Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.
• May also review vendor capability to support development.

This is a 3-6 month full time internship, 40hrs a week.

#DesignEnablement

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must be actively pursuing a MS degree with 6+ months knowledge and/or experience or PhD degree in Electrical Engineering or Computer Engineering with 1+ years of knowledge and/or experience in the following:

- VLSI and Digital Design.
- Physical Design, Place and Route Tools, Flows, and Methodology.
- Physical Design optimization algorithms.
- Artificial Intelligence and Machine Learning (AI/ML) for Physical Design.

Preferred Qualifications:

6+ months of experience/knowledge in the following:

- Power grid design and IR analysis.
- Timing budgets and analysis.
- IP block Power, Performance and Area analysis (PPA).
- EDA algorithm customization and optimization.
- Scripting language like Python, Perl or TCL.

Job Type:

Student / Intern

Shift:

Shift 1 (United States of America)

Primary Location:

Virtual US

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, Colorado, New York, Washington, California:$63,000.00-$166,000.00

S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

The application window for this job posting is expected to end by 01/24/2024