• Job Description

  Req#: JR0260355

  Job Details:

  Job Description:

  Intel's Custom Foundry division within the Technology and Manufacturing Group (TMG) is looking for: -- Runset Development Engineer that can fully develop, test, release, and support Physical Verification Runsets for external foundry customer circuit designs. In this position, your responsibilities will include but not be limited to: -- Development and support of robust and efficient Design Rule Check (DRC) and Layout Versus Schematic(LVS) runsets for advanced processes -- Development and support of complex algorithms for creating and manipulating layout design data -- Understanding of complex layout design rules and layout of complex semiconductor devices -- Debug of internal and external customer test cases -- Creation and execution of QA test cases and regression suites including both schematic and layout entry -- Creating and managing usage specification documents/whitepapers for all runset collateral. Includes, verification flows, mask layer usage, and special device templates. -- Supporting internal and external foundry design customers on runset use This is an entry level position and compensation will be given accordingly. #DesignEnablement

  Qualifications:

  Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: -Candidate must possess a bachelor's degree with 3+ months of experience or a master's degree with 6+ months in Electrical Engineering or Computer Engineering or related field. Preferred Qualifications: 3 + months in the following: - Demonstrate experience in DRC/LVS runset and algorithm development. Specific experience with Synopsys ICV and/or Mentor Calibre is a plus. - Demonstrate experience layout and/or schematic entry using Cadence Virtuoso and/or Synopsys Custom Designer. - Demonstrate experience in semiconductor device physics, models and technology scaling - Demonstrate experience and expertise with industry standard CAD tools/flows for digital and/or analog design. - Demonstrate experience with software development/programming in high-level languages (e.g. C/C++, TCL, Lisp, Perl) and CAD tool scripting languages (e.g. Cadence SKILL) - Demonstrate experience working on with UNIX/Linux platforms

  Job Type:

  College Grad

  Shift:

  Shift 1 (United States of America)

  Primary Location:

  US, Oregon, Hillsboro

  Additional Locations:

  US, California, Santa Clara

  Business group:

  As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

  Posting Statement:

  All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

  Position of Trust

  N/A

  Benefits:

  We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

  
  

  Annual Salary Range for jobs which could be performed in

  US, California:$106,231.00-$159,109.00

  S al ary range dependent on a number of factors including location and experience.

  Work Model for this Role

  This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

• About the company

  Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital world we live in.

Notice