Job Details:

Job Description:

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

• Life at Intel
• Diversity at Intel

Become part of our fast-pace and exciting IP Test Chips and Validation Team, where you’ll help get new designs onto silicon, sometimes for the very first time!

Imagine learning about a new design that have not been on silicon before or needs to be integrated into a much larger system before it goes into our next server product! You won’t do this alone! You’ll be part of our small RTL design and integration team, where we’re here to help each other grow and tape in at least one test chip per year. Most of the time, we’ll be integrating IPs but there are rare cases where we have to architect and design test chip logic that sits between an IP and off-die FPGA.

The designs we get to learn and integrate into our test chips vary since we support different groups and product spaces including, but not limited to client, server and new IPs from the labs. Sample design may include DDR, PCIe, UCIe and voltage regulator flavors to name just a few.

As an Logic/RTL Design and SOC Integration Engineer, you will be responsible for developing and debugging RTL level description of high performance and low power microprocessor.

• Responsibilities will include although not limited to:
• Contributes to definition, design, coding, verification, and documentation for SoC (System on a Chip) development.
• Determines architecture design, logic design, and system simulation.
• Defines module interfaces/formats for simulation and validation.
• Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.
• Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
• Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
• Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

The Logic/RTL Design Engineer will possess the following behavioral traits:

• Ability to learn quickly and work independently.
• Strong analytical ability, problem solving and communication skills in both written and verbal.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

What we need to see (Minimum Qualifications):

• Bachelors degree in Electrical/Computer Engineering or related field and 4+ years of experience Or a Masters degree in Electrical/Computer Engineering or related field and 3+ years of experience.
• 4+ years of RTL coding and/or IP integration experience using Verilog/SystemVerilog.
• 2+ years prior experience with Power UPF.
• 2+ years experience with common interfaces like DDR, PCIe, UCIe, HBM or other designs.
• 1+ years prior experience as IP design engineer or SOC integration engineer interfacing with IP design teams.
• 1+ years prior experience in addressing LINT, CDC and Static Timing Analysis issues.
  

How to Stand out (Preferred Qualifications):

• 8+ years of RTL coding and/or IP integration experience.
• Good integration knowledge of analog circuits and mixed signal designs.
• Create or understand logic functionalities in terms block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.
• Implement RTL in SystemVerilog, perform unit level testing, debug tests, SDC and UPF generation.
• Integrate hard IP and soft IPs including industry standard and proprietary interfaces.
• Perform RTL Lint check, RTL synthesis, Equivalence checking, CDC checking and support Static Timing Analysis.
• Ensure designs are delivered on time and with the highest quality by using proper checks.
• Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members.
• Work with verification team for test plan/strategy to meet all functional requirements and performance.
• Work with timing and physical team for timing closure and meet power and area goals.
• Support project managers with effort estimations and resource planning.
• Support team leader in coaching, training and development team members.
• Knowledge of Synthesis/Auto P&R, Primetime, post-silicon testing, etc. are a plus.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, California, Folsom, US, Oregon, Portland

Business group:

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$119,130.00-$178,690.00

S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.