• Job Description

  Req#: JR0252086

  Job Details:

  Job Description:

  Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies that will shape the future for decades to come.

  At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting-edge technologies.

  As part of the Design Enablement Process Design Kit PDK group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry-standard methods and ease of use for the end customers.

  Responsabilities are the following but not limited to:

  Creates design layouts of integrated circuit PDK testcases for a given specification and runs a set of design verification tools for process design rules, electromigration (EM), voltage drop (IR), ESD, and other checks on the layouts. Creates accurate designs that meet project needs, applying understanding of design manuals, established processes, layout elements, and basic electronic principles. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Troubleshoots a wide variety of issues up to and including layouts and tool/flow/methodology used in layout design.

  #DesignEnablement

  Qualifications:

  You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
  
  Minimum Qualifications:

  
  Candidate must possess 3+ years of physical design layout industry work experience.
  
  Preferred Qualifications:

  3+ years of experience in the following:

  
  - AA degree in VLSI or Physical Design/Mask Design.
  - Experience with layout of custom cells
  - Experience with industry-based (CAD) layout tools, for example Cadence (Virtuoso, VXL).
  - Experience in verification (ICV/Calibre DRC and LVS).
  - Experience of basic electronic circuit functionality and behaviors (passive and active circuit structures).
  - Experience layout section lead experiences.
  - Experience in analog design and layout guidelines (matching devices, symmetrical layout, signal shielding, other analog specific guidelines).

  Job Type:

  Experienced Hire

  Shift:

  Shift 1 (United States of America)

  Primary Location:

  US, Arizona, Phoenix

  Additional Locations:

  US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro

  Business group:

  As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

  Posting Statement:

  All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

  Position of Trust

  N/A

  Benefits:

  We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

  
  

  Annual Salary Range for jobs which could be performed in

  US, California:$96,470.00-$144,310.00 (Hourly Role)

  S al ary range dependent on a number of factors including location and experience.

  Work Model for this Role

  This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

• About the company

  Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital world we live in.

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