Allegro MicroSystems

Mixed Signal Verification Intern


PayCompetitive
LocationHyderabad/Telangana
Employment typeFull-Time

This job is now closed

  • Job Description

      Req#: R4808

      The Allegro team is passionate about providing intelligent solutions that move the world toward a safer and more sustainable future. With more than 30 years of experience developing advanced semiconductor technology, innovation with purpose touches every aspect of our business. From customer engagement and employee recognition to technology advancement and serving the local communities in which we maintain offices, innovation consistently drives our mission and definition of success.

      RESPONSIBILITIES

      Design Verification

      Understand the product/design requirements Prepare Verification plan documents. Testbench development using UVM Develop testcases, assertions, functional coverage. Develop scripts for running simulations

      AMS Verification:

      Understand the product/Analog module requirements Prepare Verification plan documents for Analog modules. Develop testcases using Verilog AMS, Verilog-A, WREAL, SV-RNM

      Post Silicon Validation:

      Understand the product validation requirements Prepare Validation plan document and develop testcases using Python script. Execute the validation tests on silicon, debug the issue and report them to designer. Generate Validation reports based in the silicon results.

      ESSENTIAL REQUIREMENTS

      • B.Tech/M.Tech degree in ECE/EEE/VLSI/Embedded or equivalent branch

      • Good Knowledge in Analog basics ( voltage dividers ,Op-Amp ,RC/RL filters, buffers etc.)

      • Good Knowledge in Digital design basics (Counter designs, FF, memories etc)

      • Good programming/logical skills

      • Strong knowledge in Verilog, SystemVerilog

      • Hands on experience in Analog Mixed Signal verification simulation tools, Digital simulation tools (Questasim/Cadence/VCS)

      • Knowledge in scripting like Perl/Python/Tcl/Tk

      • Good communication and documentation skills

      DESIRED QUALIFICATIONS

      • Knowledge in Universal Verification Methodology(UVM)

      • Good Knowledge in Verilog AMS, Verilog-A, WREAL, SV-RNM

      • Knowledge in assertions and functional coverage

      • Experience in Lab Automation with Instruments like Oscilloscope, Source Meter, Bench multimeters, Thermo-stream, Logic Analyzer, Spectrum Analyzer, Power Supplies, Signal Generators etc.

  • About the company

      With more than 50 years of experience developing advanced semiconductor technology and application-specific algorithms, Allegro is a global leader in power and sensing solutions for motion control and energy-efficient systems.

Notice

Talentify is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.

Talentify provides reasonable accommodations to qualified applicants with disabilities, including disabled veterans. Request assistance at accessibility@talentify.io or 407-000-0000.

Federal law requires every new hire to complete Form I-9 and present proof of identity and U.S. work eligibility.

An Automated Employment Decision Tool (AEDT) will score your job-related skills and responses. Bias-audit & data-use details: www.talentify.io/bias-audit-report. NYC applicants may request an alternative process or accommodation at aedt@talentify.io or 407-000-0000.