Job Details:

Job Description:

Responsibilities included but not limited to the followings:

• Defining and developing Assembly Test Chips used to certify new Intel processes.
• Responsible for leading the definition and development of Assembly Test Chips/Design Rules used to certify next gen package concepts and architectures and for IFS customers.
• Owns definition and design of Full loop Assembly Test chips used to understand chip-package interactions for package technologies.
• As part of this job role, the candidate will be required to work with other partners within ATTD/Fab/Foundry to define test chip floorplans and coordinate layout.
• Provides design solutions in test chips for ESD protections, incorporating basic IP blocks, generating DR compliant layouts on full metal stacks on Intel 16 or newer nodes.

The candidate should also exhibit the following behavioral traits:

• Proven team player with demonstrated collaboration with customers.
• Willingness to work independently with good listening, written and verbal communication/presentation skills.

Qualifications:

For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information .

You must possess the below requirements to be initially considered for this position.

Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

• Must possess a Masters Degree with 2+ years of experience or PHD in electrical, mechanical, material science or related field.
• Experience with Cadence Virtuoso suite of tools
• Familiarity with assembly processes, chip package interaction.
• Experience with DRC/DFM for Intel 16 process node and beyond.
• Experience with full chip integration and device tape-in using Cadence Virtuoso.

Preferred Qualifications:

• Experience with other Si EDA platforms such as Synopsys ICC/ICWorkbench and SKILL scripting is a plus

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, Oregon, Hillsboro

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.