Cadence Design Systems
Principal Design Engineer
PayCompetitive
LocationNoida/Uttar Pradesh
Employment typeFull-Time
What's your preference?
Job Description
- Req#: R44818
- Master degree in Electrical Engineering with 6 + years of experience or bachelor degree with 8+ years
- Experience with FPGA design and verification using Verilog
- Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route
- Experience in debugging FPGAs in the lab using Vivado hardware manager
- Experience using Linux servers, Script development using Shell/Perl/TCL
- Experience using Cadence Simulators Incisive or Xcellium
- Detailed knowledge about one or more industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI desired.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This position is in HSV (Hardware System Verification) group in the SVG (System Verification Group) of Cadence. The team is working on Protium - FPGA based prototyping platforms.
Team is responsible for developing FPGA IPs for Protium platform, including architecture, design, verification, integration, timing closure, documentation and releasing the IPs to end users.
The Principal Design Engineer is responsible for FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware.
Enhancements to current IPs as well as developing new IPs.
Required experience:
We’re doing work that matters. Help us solve what others can’t.
About the company
Cadence Design Systems, Inc., headquartered in San Jose, California, in the North San Jose Innovation District, is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Sy...