Jabil
Principal FPGA Verification Engineer (On-site Warren, NJ)
This job is now closed
Job Description
- Req#: J2354923
- Proficiency in System Verilog, Verilog, UVM, and assertion-based verification
- Expert knowledge of Xilinx Vivado and Questa simulator
- Lead verification planning from specifications and system requirements
- Create, execute, and track detailed verification test plans
- Develop automated regression test suites
- Create and enhance constrained-random verification environments
- Develop scalable verification automation environment in Git
- Work with RTL designers to identify verification goals and define test strategies
- Facilitate testing of RTL against reference MATLAB and C models
- Perform Failure Analysis and collect and report coverage matrices
- Support Radio Head testing by collaborate with members of Hardware, Software, System Test, and Manufacturing teams
- Experience with protocol compliance verification, functional/code coverage evaluation.
- Experience with wireless communication systems and digital signal processing
- Some experience with FPGA design/synthesis, constraints, and timing closure
- Familiar with Linux, Embedded C programming, scripting languages (TCL, Python, Bash, etc.)
- Understanding of SoC Processor Subsystem to support software developers
- Mentor junior verification engineers
- QEMU/C based co-simulation in Vivado
- ORAN specification
- MATLAB
At Jabil we strive to make ANYTHING POSSIBLE and EVERYTHING BETTER. With over 260,000 diverse, talented and dedicated employees across 100 locations in 30 countries, our vision is to be the most technologically advanced and trusted manufacturing solutions provider. We combine an unmatched breadth and depth of end-market experience, technical and design capabilities, manufacturing know-how, supply chain insights and global product management expertise to enable success for the world’s leading brands. We are driven by a common purpose to make a positive impact for each other, our communities, and the environment.
JOB SUMMARY
The Principal FPGA verification engineer will architect and develop UVM based verification environments for ORAN compliant 4G and 5G radio products. This will include developing and documenting end-to-end verification test-benches, creating test plans, and executing test cases. The candidate will also perform hardware validation and debug on hardware platforms.
The candidate should have a solid background in UVM and assertion-based verification using System Verilog and demonstrated ability to write, test and debug code independently. Expertise with Xilinx Vivado simulator and Questa is highly desired. ***Note, this is an On-site position at our Warren, NJ location, with option of a Hybrid work situation once on board with our team in Warren.***
ESSENTIAL DUTIES AND RESPONSIBILITIESExperience with the following is a plus:
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JOB QUALIFICATIONS-
EDUCATION & EXPERIENCE REQUIREMENTS
· Masters degree in Engineering from an accredited four-year college or university
· Minimum 10+ years of related experience (3+ years’ experience with UVM preferred)
· Minimum of 2 years experience as a Lead EngineerJabil, including its subsidiaries, is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, national origin, sex, sexual orientation, gender identity, age, disability, genetic information, veteran status, or any other characteristic protected by law.
About the company
Jabil Inc. is an American worldwide manufacturing services company.