Job Details:

Job Description:

About Advanced Design:
The Advanced Design organization delivers critical technology and design collaterals to enable future product designs. Critical to our mission, AD develops the first chips for all new Intel technology nodes. Intel prides to ensure process and design enablement are robust for high-volume product manufacturing.

The Group:
You will be part of Intel's Advanced Design Organization (AD) within Design Enablement (DE), focused on memory design and pathfinding where you will develop advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.

The Role:
As a member of our team, your responsibilities will include (but not limited to):

• Custom digital memory circuit design.
• Memory pathfinding.
• Power performance area (PPA) optimization through design technology co-optimization (DTCO).
• Product/design enablement.
• Bitcell and periphery layout design.
• Process design kit enablement and support.
• Design Automation.
• Memory array/IP design, memory circuit innovation, testchip design, execution, and validation.
• Pre- and post-Si validation and debug to enable yield and parametric tracking and ramp.

#DesignEnablement

Qualifications:

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must possess a BS with 3+ years of experience or MS degree with 2+ years of experience or PhD with 1+ years of experience in Electrical Engineering, Computer Engineering or related field.

Experience in the following:

• Custom digital memory circuit design
• Custom circuit simulation and verification
• Custom layout design and verification
• Static timing analysis
• ASIC design flow and validation
• Industry standard CAD tools and flows for digital and/or analog design
• Device physics

Preferred Qualification:

2+ years of experience in the following:

• Design, characterization, and verification of custom memory circuits and arrays such as SRAM, Register File, and ROM.
• Design trade-off of power, performance, and area

Design technology co-optimization

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

Virtual US

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, Colorado, New York, Washington, California:$119,130.00-$178,690.00

S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.