At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Bachelor's or Master's degree in ECE or equivalent
• Proficiency in computer architecture and hardware design
• Experience in Object-Oriented Programming with C++ and/or SystemVerilog, and strong coding skills
• Knowledgeable in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Exposure to design and verification tools, and methodologies (UVM or equivalent)
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
• 3+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
• 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Education : BE/BTech/ME/MTech or equivalent
Experience : 3 to 7 years

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