Cadence Design Systems
Lead Verification Design Engineer
PayCompetitivo
LocationNoida/Uttar Pradesh
Employment typeFull-Time
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Job Description
- Req#: R46242
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- 4+ years of Design Verification experience with SV/UVM
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage
We’re doing work that matters. Help us solve what others can’t.
About the company
Cadence Design Systems, Inc., headquartered in San Jose, California, in the North San Jose Innovation District, is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Sy...