Marvell
Link Layer architect
This job is now closed
Job Description
- Req#: 2601002
Define and develop link layer architectures for various high-speed interconnects (Ethernet and custom link - layers )
Drive link layer architecture in the context of full-system performance, power, reliability and scalability goals
Create architectural specifications and design documents for link layer protocols and implementations
Drive technical decisions on link layer features including error correction, flow control, retry mechanisms, and data integrity
Evaluate and recommend new link layer technologies and standards for next-generation products and custom solutions
Lead architecture reviews and provide technical guidance to cross-functional teams
Define interfaces between link layer, transaction layer, and physical layer
Optimize link efficiency, latency, and bandwidth utilization
Stay current with emerging link layer standards and technologies
Contribute to specification development and review
Ensure compliance with industry standards and specifications
Engage directly with customers on architecture discussions, including requirements definition, architectural alignment, and design trade-offs
Work closely with PHY architects, system architects, and ASIC design teams
Partner with verification teams to define test plans and coverage strategies
Support hardware bring-up and validation teams with technical expertise
Research and evaluate new link layer technologies and approaches
Develop proof-of-concept implementations for novel link layer features
Create reusable IP blocks and architectural frameworks
Drive continuous improvement in link layer performance and reliability
Create comprehensive architecture specifications and design documentation
Develop datasheets, integration guides, and reference designs
Present technical concepts to internal teams and external customers
Mentor engineers and share link layer expertise across the organization
Extensive experience (typically 10+ years) in link-layer design and architecture
Deep understanding of Ethernet link layer IEEE 802.3 (100G and 200G )
Strong knowledge of link layer protocols, error detection/correction, and reliability mechanisms
Experience with FEC implementations (Reed-Solomon, Hamming, BCH, etc.)
Understanding of link training, equalization, and physical layer interaction
Proven track record of defining successful system architectures
Experience guiding RTL design and verification, including design reviews and architectural trade-offs (hands-on experience a plus)
Understanding of SerDes/PHY interfaces and requirements
Excellent written and verbal communication skills
Ability to present complex technical concepts to diverse audiences
Experience leading cross-functional technical initiatives
Strong problem-solving and analytical capabilities
MS or PhD in Electrical Engineering, Computer Engineering, or related field
Experience with chiplet architectures and advanced packaging
Prior involvement in industry standards organizations
Knowledge of network protocol stacks and system architecture
Strategic thinking and long-term technology planning
Innovation and creative problem-solving
Collaborative and team-oriented approach
Customer focus and business acumen
Adaptability to emerging technologies
Attention to detail and quality
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell’s Compute and Custom Solutions organization (CCS) is looking for a talented senior ASIC link layer architect to join our architecture team. This team acts as the central technical interface to our datacenter clients. It is responsible for the overall technology choice, silicon partitioning strategy, IP definition and selection and architectural guidance of datacenter products (SmartNIC, servers, AI accelerators and switches, mainly) for the main hyperscalers and companies worldwide. We actively participate in the definition of next generation datacenter products with our clients and respond to their ASIC RFQs. Role spans engagement with both customers and internal technology teams to define the best solution to the custom product needs and includes all functions required to build, test and manufacture an advanced custom silicon System in a Package.What You Can Expect
We are seeking a senior Link Layer Architect to own the end-to-end architecture of link layer solutions across high-speed interconnect protocols including Ethernet, Cus tom link- layers and Die-to-Die (D2D) interfaces.
This role offers the opportunity to shape the future of high-speed interconnect technologies at Marvell, engaging with customers to enable next-generation computing and communication systems as an integral part of the Custom Solutions Architecture team .
Architecture & Technical Leadership
System Integration & Optimization
Standards & Industry Engagement
Cross-Functional Collaboration
Innovation & Technology Development
Documentation & Knowledge Sharing
What We're Looking For
Technical Expertise
Architecture Skills
Communication & Leadership
Preferred Qualifications
Key Competencies
Expected Base Pay Range (USD)
191,530 - 286,900, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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About the company
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